A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. Many phases of electronic design activities may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may uses a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters.
Typically, geometric information about the placement of the nodes and components onto the chip is determined by a placement process and a routing process. The placement process is a process for placing electronic components or circuit blocks on the chip and the routing process is the process for creating interconnections between the blocks and components according to the specified netlist. Based upon this geometric information, photomasks are created for lithographic manufacturing of the electronic product. A photomask, or more simply a “mask,” provides the master image of one layer of a given integrated chip's physical geometries. A typical photolithography system projects UV light energy on to and through the mask in order to transmit the mask pattern in reduced size to the wafer surface, where it interacts with a photosensitive coating on the wafer.
Significant variations may arise during the process of manufacturing the IC. For example, lithography mask creation and printing assume that projection is done on a film, within a predetermined depth of focus range. However pattern dependencies between the process by which the ICs are fabricated and the pattern that is being created often cause processed films to have significant variation in thickness across a surface, resulting in variation in feature dimensions (e.g. line widths) of ICs that are patterned using the mask.
Lithography models may be created and used by EDA tools during many phases of the electronic design process, such as physical design, implementation, and verification. These models incorporate numerous mathematical matrices that relate to physical structures within the electronic design. However, using conventional approaches, it is often very difficult to determine the correct number of matrices that should be used for an optical lithography model. It is generally noted that the more matrices that are used, the more accurate is the model. The problem is that more matrices that are used, the more time and resources are needed to work upon the model by later EDA applications. Therefore, it is desired to be able to implement the model to be both as simple as possible and as accurate as possible. Clearly there is a tension between these two goals.
One possible approach is to allow the user to specifically select the number of matrices to use for the model. The problem with this approach is that in most cases, this method of selecting the number of matrices really is a result of the user guessing at the number of matrices that is needed. This guess is highly based highly subject to errors and wrong assumptions.
Another approach is to use the “forward analysis” approach. The forward analysis approach first requires the system to compute the entire set of matrices that the system can compute. The approach then work “backwards” to determine which set of matrices will produce the desired accuracy. The problem with this approach is that it is very resource intensive and may use an excessive amount of time and effort.
As is evident, there is a great need for a better approach to generate a lithography model, which can efficiently and accurately determine the number of matrices to use for the model.